1. Field of the Invention
The present invention relates to stacked LSIs.
2. Background Art
Performances of LSIs have been improved by integrating more and more transistors on one chip with the advance of the microfabrication technology. However, it will not necessarily be an optimum solution to increase the number of transistors integrated on one chip as before, because of the limitations of miniaturization and increase in cost of using cutting-edge processes. Therefore, three-dimensional integration in which multiple LSIs are stacked will be promising technology.
In such 3D integration, communication capability among the stacked LSIs and between the stacked LSIs and an external device is important. As communication methods for stacked LSIs, wired (a method of providing electrodes (via) in an LSI silicon board) and wireless methods are being studied.
In sophisticated media processing and network processing in these days, the transfer capacity between an LSI including a CPU and other components and a memory is increasing year by year and the performance of communication between these components is becoming the key factor that determines the overall performance. JP Patent Publication (Kokai) No. 2004-327474 makes reference to a configuration in which an LSI that provides communication between a memory and a component on a board as well as multiple memory LSIs are stacked. By stacking multiple memories provided on a plane of the system board, wiring lines to the memories can be shorten, contributing to speed enhancement and reduction in power consumption.